Technical Field
This disclosure relates generally to improved semiconductor memory devices and methods for making such devices.
Related Art
The storage capacity of a memory device depends on a number of memory cells included in the memory device, while the physical size of the memory device depends on the proximity of the memory cells to one another. It is usually desirable to either increase the storage capacity of the memory device while keeping the physical size of the memory device unchanged, or decrease the physical size of the memory device while keeping the storage capacity of the memory device unchanged. Either of these two cases may be achieved by minimizing the spacing between adjacent memory cells in a memory array, while concurrently providing adequate spacing for electrical contacts and maintaining the required electrical isolation between the adjacent memory cells and the electrical contacts. However, the spacing between adjacent memory cells is limited by the aspect ratio of the gates of the memory cells. The lower the aspect ratio of the adjacent gates, the closer the gates can be to each other.
What is needed are semiconductor devices and methods for manufacturing them that result in memory cells having gates of relatively low aspect ratio such that the spacing between the adjacent cells can be minimized, while maintaining the required electrical isolation between the gates and the contacts.